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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad977/ad977a one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 16-bit, 100 ksps/200 ksps bicmos a/d converter functional block diagram pwrd sync dataclk data 2r r1 in r2 in r3 in ref v ana 4k dgnd tag r/ ccs v dig agnd2 cap agnd1 switched cap adc 4r ad977/ ad977a r = 5k ad977 r = 2.5k ad977a 4r r 2.5v reference busy serial data interface control logic & internal calibration circuitry clock sb/ btc ext/ int features fast 16-bit adc 100 ksps throughput ratead977 200 ksps throughput ratead977a single 5 v supply operation power dissipation 100 mw max power-down mode 50 w input ranges: unipolar; 0 vC10 v, 0 vC5 v and 0 vC4 v bipolar; 10 v, 5 v and 3.3 v choice of external or internal 2.5 v reference high speed serial interface on-chip clock 20-lead skinny dip or soic package 28-lead skinny ssop package general description the ad977/ad977a is a high speed, low power 16-bit a/d converter that operates from a single 5 v supply. the ad977a has a throughput rate of 200 ksps whereas the ad977 has a throughput rate of 100 ksps. each part contains a successive approximation, switched capacitor adc, an internal 2.5 v reference, and a high speed serial interface. the adc is factory calibrated to minimize all linearity errors. the ad977/ad977a is specified for full scale bipolar input ranges of 10 v, 5 v and 3.3 v, and unipolar ranges of 0 v to 10 v, 0 v to 5 v and 0 v to 4 v. the ad977/ad977a is comprehensively tested for ac param- eters such as snr and thd, as well as the more traditional dc parameters of offset, gain and linearity. product highlights 1. fast throughput the ad977/ad977a is a high speed, 16-bit adc based on a factory calibrated switched capacitor architecture. 2. single-supply operation the ad977/ad977a operates from a single 5 v supply and dissipates only 100 mw max. 3. comprehensive dc and ac specifications in addition to the traditional specifications of offset, gain and linearity, the ad977/ad 977a is fully tested for snr and thd.
ad977/ad977a C2C rev. d a grade b grade c grade parameter min typ max min typ max min typ max unit resolution 16 16 16 bits analog input voltage range 10 v, 0 v to 5 v, . . . (see table ii) impedance see table ii sampling capacitance 40 40 40 pf throughput speed complete cycle 10 10 10 s throughput rate 100 100 100 khz dc accuracy integral linearity error 3 2.0 3 lsb 1 differential linearity error C2 +3 C1 +1.75 2 lsb no missing codes 15 16 15 bits transition noise 2 1.0 1.0 1.0 lsb full-scale error 3, 4 0.5 0.25 0.5 % full-scale error drift 7 7 7 ppm/ c full-scale error ext. ref = 2.5 v 0.5 0.25 0.5 % full-scale error drift ext. ref = 2.5 v 2 2 2 ppm/ c bipolar zero error 3 bipolar ranges 10 10 15 mv bipolar zero error drift bipolar ranges 2 2 2 ppm/ c unipolar zero error 3 unipolar ranges 10 10 10 mv unipolar zero error drift unipolar ranges 2 2 2 ppm/ c recovery to rated accuracy after power-down 5 2.2 f to cap 1 1 1 ms power supply sensitivity v ana = v dig = v d = 5 v 5% 8 8 8 lsb ac accuracy spurious free dynamic range 6 90 96 90 db 7 total harmonic distortion 6 C90 C96 C90 db signal-to-(noise+distortion) 6 83 85 83 db C60 db input 27 28 27 db signal-to-noise 6 83 85 83 db full power bandwidth 8 700 700 700 khz C3 db input bandwidth 1.5 1.5 1.5 mhz sampling dynamics aperture delay 40 40 40 ns transient response, full-scale step 2 2 2 s overvoltage recovery 9 150 150 150 ns reference internal reference voltage 2.48 2.5 2.52 2.48 2.5 2.52 2.48 2.5 2.52 v internal reference source current 1 1 1 a external reference voltage range for specified linearity 2.3 2.5 2.7 2.3 2.5 2.7 2.3 2.5 2.7 v external reference current drain ext. ref = 2.5 v 100 100 100 a notes 1 lsb means least significant bit. with a 10 v input, one lsb is 305 v. 2 typical rms noise at worst case transitions and temperatures. 3 measured with fixed resistors as shown in figures 11, 12 and 13. adjustable to zero. tested at room temperature. 4 full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full scal e transition voltage, and includes the effect of offset error. for bipolar input ranges, the full-scale error is the worst case of either the Cfull scale or +full scale code transitio n voltage errors. for unipolar input ranges, full-scale error is with respect to the +full-scale code transition voltage. 5 external 2.5 v reference connected to ref. 6 f in = 20 khz, 0.5 db down unless otherwise noted. 7 all specifications in db are referred to a full scale 10 v input. 8 full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise+distortion) degrades to 60 db, or 10 bi ts of accuracy. 9 recovers to specified performance after a 2 f s input overvoltage. specifications subject to change without notice. ad977?pecifications (?0 c to +85 c, f s = 100 khz, v dig = v ana = 5 v, unless otherwise noted)
C3C rev. d ad977/ad977a a grade b grade c grade parameter min typ max min typ max min typ max unit resolution 16 16 16 bits analog input voltage range 10 v, 0 v to 5 v, . . . (see table ii) impedance see table ii sampling capacitance 40 40 40 pf throughput speed complete cycle 5 5 5 s throughput rate 200 200 200 khz dc accuracy integral linearity error 3 2.0 3 lsb 1 differential linearity error C2 +3 C1 +1.75 2lsb no missing codes 15 16 15 bits transition noise 2 1.0 1.0 1.0 lsb full-scale error 3, 4 0.5 0.25 0.5 % full-scale error drift 7 7 7 ppm/ c full-scale error ext. ref = 2.5 v 0.5 0.25 0.5 % full-scale error drift ext. ref = 2.5 v 2 2 2 ppm/ c bipolar zero error 3 bipolar ranges 10 10 15 mv bipolar zero error drift bipolar ranges 2 2 2 ppm/ c unipolar zero error 3 unipolar ranges 10 10 10 mv unipolar zero error drift unipolar ranges 2 2 2 ppm/ c recovery to rated accuracy after power-down 5 2.2 f to cap 1 1 1 ms power supply sensitivity v ana = v dig = v d = 5 v 5% 8 8 8lsb ac accuracy spurious free dynamic range 6 90 96 90 db 7 total harmonic distortion 6 C90 C96 C90 db signal-to-(noise+distortion) 6 83 85 83 db C60 db input 27 28 27 db signal-to-noise 6 83 85 83 db full power bandwidth 8 1 1 1 mhz C3 db input bandwidth 2.7 2.7 2.7 mhz sampling dynamics aperture delay 40 40 40 ns transient response, full-scale step 1 1 1 s overvoltage recovery 9 150 150 150 ns reference internal reference voltage 2.48 2.5 2.52 2.48 2.5 2.52 2.48 2.5 2.52 v internal reference source current 1 1 1 a external reference voltage range for specified linearity 2.3 2.5 2.7 2.3 2.5 2.7 2.3 2.5 2.7 v external reference current drain ext. ref = 2.5 v 1.2 1.2 1.2 ma notes 1 lsb means least significant bit. with a 10 v input, one lsb is 305 v. 2 typical rms noise at worst case transitions and temperatures. 3 measured with fixed resistors as shown in figures 11, 12 and 13. adjustable to zero. tested at room temperature. 4 full-scale error is expressed as the % difference between the actual full-scale code transition voltage and the ideal full scal e transition voltage, and includes the effect of offset error. for bipolar input ranges, the full-scale error is the worst case of either the Cfull scale or +full scale code transitio n voltage errors. for unipolar input ranges, full-scale error is with respect to the +full-scale code transition voltage. 5 external 2.5 v reference connected to ref. 6 f in = 20 khz, 0.5 db down unless otherwise noted. 7 all specifications in db are referred to a full scale 10 v input. 8 full-power bandwidth is defined as full-scale input frequency at which signal-to-(noise+distortion) degrades to 60 db, or 10 bi ts of accuracy. 9 recovers to specified performance after a 2 f s input overvoltage. specifications subject to change without notice. ad977a?pecifications (?0 c to +85 c, f s = 200 khz, v dig = v ana = 5 v, unless otherwise noted)
C4C rev. d ad977/ad977a?pecifications (both specs) a, b, c grades parameter conditions min typ max unit digital inputs logic levels v il C0.3 +0.8 v v ih 2.0 v dig + 0.3 v i il 10 a i ih 10 a digital outputs data format serial 16-bits data coding binary twos complement or straight binary pipeline delay conversion results only available after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = 500 a4 v power supplies specified performance v dig 4.75 5 5.25 v v ana 4.75 5 5.25 v i dig 4ma i ana 11 ma power dissipation pwrd low 100 mw pwrd high 50 w temperature range specified performance t min to t max C40 +85 c specifications subject to change without notice. timing specifications ad977a ad977 symbol min typ max min typ max unit convert pulsewidth t 1 50 50 ns r/ c , cs to busy delay t 2 83 83 ns busy low time t 3 4.0 8.0 s busy delay after end of conversion t 4 50 50 ns aperture delay t 5 40 40 ns conversion time t 6 3.8 4.0 7.6 8.0 s acquisition time t 7 1.0 2.0 s throughput time t 6 + t 7 510 s r/ c low to dataclk delay t 8 220 350 ns dataclk period t 9 220 450 ns data valid setup time t 10 50 100 ns data valid hold time t 11 20 20 ns ext. dataclk period t 12 66 100 ns ext. dataclk high t 13 20 20 ns ext. dataclk low t 14 30 30 ns r/ c , cs to ext. dataclk setup time t 15 20 t 12 + 5 20 t 12 + 5 ns r/ c to cs setup time t 16 10 10 ns ext. dataclk to sync delay t 17 15 66 15 66 ns ext. dataclk to data valid delay t 18 25 66 25 66 ns cs to ext. dataclk rising edge delay t 19 10 10 ns previous data valid after cs , r/ c low t 20 3.5 7.5 s busy to ext. dataclk setup time t 21 55ns final ext. dataclk to busy rising edge t 22 1.7 3.5 s tag valid setup time t 23 00ns tag valid hold time t 24 20 20 ns specifications subject to change without notice. (ad977a: f s = 200 khz, ad977: f s = 100 khz, v dig = v ana = 5 v, ?0 c to +85 c)
ad977/ad977a C5C rev. d caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad977/ad977a feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 analog inputs r1 in , r2 in , r3 in . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v cap . . . . . . . . . . . . . . . . .+v ana + 0.3 v to agnd2 C 0.3 v ref . . . . . . . . . . . . . . . . . . . . . indefinite short to agnd2, . . . . . . . . . . . . . . . . . . . . . . . . . momentary short to v ana ground voltage differences dgnd, agnd1, agnd2 . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages v ana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dig to v ana . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v digital inputs . . . . . . . . . . . . . . . . . . . C0.3 v to v dig + 0.3 v internal power dissipation 2 pdip (n), soic (r), ssop (rs) . . . . . . . . . . . . . 700 mw junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range n, r . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 20-lead pdip: ja = 100 c/w, jc = 31 c/w, 20-lead soic: ja = 75 c/w, jc = 24 c/w, 28-lead ssop: ja = 109 c/w, jc = 39 c/w. pin configurations sb/btc ext/int cs busy r/c 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad977 ad977a v dig v ana pwrd tag data dataclk sync r1 in agnd1 r2 in r3 in cap ref agnd2 dgnd 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad977 ad977a nc = no connect v dig v ana pwrd nc nc nc tag nc data dataclk sync r1 in agnd1 r2 in r3 in nc cap ref nc agnd2 nc nc dgnd r/c cs busy sb/btc ext/int soic and dip ssop 1.6ma i ol 500 ai oh 1.4v c l 100pf to output pin figure 1. load circuit for digital interface timing ordering guide temperature throughput package model range rate max inl min s/(n+d) options * ad977an C40 c to +85 c 100 ksps 3.0 lsb 83 db n-20 ad977bn C40 c to +85 c 100 ksps 2.0 lsb 85 db n-20 ad977cn C40 c to +85 c 100 ksps 83 db n-20 ad977aan C40 c to +85 c 200 ksps 3.0 lsb 83 db n-20 ad977abn C40 c to +85 c 200 ksps 2.0 lsb 85 db n-20 ad977acn C40 c to +85 c 200 ksps 83 db n-20 ad977ar C40 c to +85 c 100 ksps 3.0 lsb 83 db r-20 ad977br C40 c to +85 c 100 ksps 2.0 lsb 85 db r-20 ad977cr C40 c to +85 c 100 ksps 83 db r-20 ad977aar C40 c to +85 c 200 ksps 3.0 lsb 83 db r-20 ad977abr C40 c to +85 c 200 ksps 2.0 lsb 85 db r-20 ad977acr C40 c to +85 c 200 ksps 83 db r-20 ad977ars C40 c to +85 c 100 ksps 3.0 lsb 83 db rs-28 AD977BRS C40 c to +85 c 100 ksps 2.0 lsb 85 db rs-28 ad977crs C40 c to +85 c 100 ksps 83 db rs-28 ad977aars C40 c to +85 c 200 ksps 3.0 lsb 83 db rs-28 ad977abrs C40 c to +85 c 200 ksps 2.0 lsb 85 db rs-28 ad977acrs C40 c to +85 c 200 ksps 83 db rs-28 * n = 20-lead 300 mil plastic dip; r = 20-lead soic; rs = 28-lead ssop. warning! esd sensitive device
ad977/ad977a C6C rev. d pin function descriptions pin no. pin no. dip/soic ssop mnemonic description 1, 3, 4 1, 3, 4 r1 in , r2 in , r3 in analog input. refer to table i, table ii for input range configuration. 2 2 agnd1 analog ground. used as the ground reference point for the ref pin. 5 6 cap reference buffer output. connect a 2.2 f tantalum capacitor between cap and analog ground. 6 7 ref reference input/output. the internal 2.5 v reference is available at this pin. alternatively an external reference can be used to override the internal reference. in either case, connect a 2.2 f tantalum capacitor between ref and analog ground. 7 9 agnd2 analog ground. 8 12 sb/ btc this digital input is used to select the data format of a conversion result. with sb/ btc tied low, conversion data will be output in binary twos complement form at. with sb/ btc connected to a logic high, data is output in straight binary format. 9 13 ext/ int digital select input for choosing the internal or an external data clock. with ext/ int tied low, after initiating a conversion, 16 dataclk pulses transmit the previous conversion result as shown in figure 3. with ext/ int set to a logic high, output data is synchronized to an external clock signal connected to the dataclk input. data is output as indicated in figure 4 through figure 9. 10 14 dgnd digital ground. 11 15 sync d igital output frame synchronization for use with an external data clock (ext/ int = logic high). when a read sequence is initiated, a pulse one dataclk period wide is output synchronous to the external data clock. 12 16 dataclk serial data clock input or output, dependent upon the logic state of the ext/ int pin. when using the internal data clock (ext/ int = logic low), a conversion start sequence will initiate transmission of 16 dataclk periods. output data is synchronous to this clock and is valid on both its rising and falling edges (figure 3). when using an external data clock (ext/ int = logic high), the cs and r/ c signals control how conversion data is accessed. 13 17 data the serial data output is synchronized to dataclk. conversion results are stored in an on-chip register. the ad977 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of sb/ btc . when using the internal data clock (ext/ int = logic low), data is valid on both the rising and falling edges of dataclk. between conversions data will remain at the level of the tag input when the conversion was started. using an external data clock (ext/ int = logic high) allows previous conversion data to be accessed during a conversion (figures 5, 7 and 9) or the conversion result can be accessed after the completion of a conversion (figures 4, 6 and 8). 14 19 tag this digital input can be used with an external data clock, (ext/ int = logic high) to daisy chain the conversion results from two or more ad977s onto a single data line. the digital data level on tag is output on data with a delay of 16 or 17 external dataclk periods after the initiation of the read sequence. dependent on whether a sync is not present or present. 15 21 r/ c read/convert input. is used to control the conversion and read modes of the ad977. with cs low; a falling edge on r/ c holds the analog input signal inter- nally and starts a conversion, a rising edge enables the transmission of the conver- sion result. 16 24 cs chip select input. with r/ c low, a falling edge on cs will initiate a conversion. with r/ c high, a falling edge on cs will enable the serial data output sequence. 17 25 busy busy output. goes low when a conversion is started, and remains low until the conversion is completed and the data is latched into the on-chip shift register. 18 26 pwrd power-down input. when set to a logic high power consumption is reduced and conversions are inhibited. the conversion result from the previous conversion is stored in the onboard shift register. 19 27 v ana analog power supply. nominally 5 v. 20 28 v dig digital power supply. nominally 5 v.
ad977/ad977a C7C rev. d definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last + transition (from 011 . . . 10 to 011 . . . 11 for twos complement format) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (9.9995422 v for a 10 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. bipolar zero error bipolar zero error is the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. unipolar zero error in unipolar mode, the first tr ansition should occur at a level 1/2 lsb above analog ground. unipolar zero error is the devia- tion of the actual transition from that point. spurious free dynamic range the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of a full-scale input signal and is expressed in decibels. signal to (noise and distortion) (s/[n+d]) ratio s/(n+d) is the ratio of the rms value of the measu red input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. full power bandwidth the full power bandwidth is defined as the full-scale input fre- quency at w hich the s/(n+d) degrades to 60 db, 10 bits of accuracy. aperture delay aperture delay is a measure of the acquisition performance, and is measured from the falling edge of the r/ c input to when the input signal is held for a conversion. transient response the time required for the ad977/ad977a to achieve its rated accuracy after a full-scale step function is applied to its input. overvoltage recovery the time required for the adc to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value.
ad977/ad977a C8C rev. d conversion control the ad977/ad977a is controlled by two signals: r/ c and cs . when r/ c is brought low, with cs low, for a minimum of 50 ns, the input signal will be held on the internal capacitor array and a conversion n will begin. once the conversion process does begin, the busy signal will go low until the conversion is com- plete. internally, the signals r/ c and cs are ord together and there is no requirement on which signal is taken low first when initiating a conversion. the only requirement is that there be at least 10 ns of delay between the two signals being taken low. after the conversion is complete the busy signal will return high and the ad977/ad977a will again resume tracking the input signal. under certain conditions the cs pin can be tied low and r/ c will be used to determine whether you are initiat- ing a conversion or reading data. on the first conversion, after the ad977/ad977a is powered up, the data output will be indeterminate. conversion results can be clocked serially out of the ad977/ ad977a using either an internal clock, generated by the ad977/ad977a, or by using an external clock. the ad977/ ad977a is configured for the internal data clock mode by pull- ing the ext/ int pin low. it is configured for the external clock mode by pulling the ext/ int pin high. internal data clock mode the ad977/ad977a is configured to generate and provide the data clock when the ext/ int pin is held low. typically cs will be tied low and r/ c will be used to initiate a conversion n. during the conversion the ad977/ad977a will output 16 bits of data, msb first, from conversion n-1 on the data pin. this data will be synchronized with 16 clock pulses provided on the dataclk pin. the output data will be valid on both the rising and falling edge of the data clock as shown in figure 3. after the lsb has been presented, the data pin will assume whatever state the tag input was at during the start of con- version, and the dataclk pin will stay low until another conversion is initiated. external data clock mode the ad977/ad977a is configured to accept an externally sup- plied data clock when the ext/ int pin is held high. this mode of operation provides several methods by which conversion results can be read from the ad977/ad977a. the output data from conversion n-1 can be read during conversion n, or the output data from conversion n can be read after the conver- sion is complete. the external clock can be either a continuous or discontinuous clock. a discontinuous clock can be either t 1 t 3 t 2 t 5 t 6 t 4 t 7 cs, r/c mode acquire convert acquire convert busy figure 2. basic conversion timing busy r/c t 8 t 11 t 6 dataclk t 1 t 9 t 10 msb valid bit 14 valid bit 13 valid bit 1 valid lsb valid t 2 123 1516 data figure 3. serial data timing for reading previous conversion results with internal clock ( cs , ext/ int and tag set to logic low)
ad977/ad977a C9C rev. d normally low or normally high when i nactive. in the case of the discontinuous clock, the ad977/ad977a can be configured to either generate or not generate a sync output (with a continu- ous clock a sync output will always be produced). each of the methods will be described in the following sections and are illustrated in figures 4 through 9. it should be noted that all timing diagrams assume that the receiving device is latching data on the rising edge of the external clock. if the falling edge of dataclk is used then, in the case of a discon- tinuous clock, one less clock pulse is required than shown in figures 4 through 7 to latch in a 16-bit word. note that data is valid on the falling edge of a clock pulse (for t 13 greater than t 18 ) and the rising edge of the next clock pulse. the ad977 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion cycle. normally the occurrence of an incorrect bit decision during a conversion cycle is irreversible. this error occurs as a result of noise during the time of the decision or due to insufficient settling time. as the ad977/ad977a is perform- ing a conversion it is important that transitions not occur on digital input/output pins or degradation of the conversion result could occur. this is particularly important during the second half of the conversion process. for this reason it is recommended that when an external clock is being provided it be a discontinu- ous clock that is not toggling during the time that busy is low or, more importantly, that it does not transition during the latter half of busy low. external discontinuous clock data read after conversion no sync output generated figure 4 illustrates the method by which data from conversion n can be read after the conversion is complete using a discon- tinuous external clock without the generation of a sync output. after a conversion is complete, indicated by busy returning high, the result of that conversion can be read while cs is low and r/ c is high. in this mode cs can be tied low. the msb will be valid on the first falling edge and the second rising edge of dataclk. the lsb will be valid on the 16th falling edge and the 17th rising edge of dataclk. a mini- mum of 16 clock pulses are required for dataclk if the receiving device will be latching data on the falling edge of dataclk. a minimum of 17 clock pulses are required for dataclk if the receiving device will be latching data on the rising edge of dataclk. approximately 40 ns after the 17th rising edge of dataclk (if provided) the data output pin will reflect the state of the tag input pin during the first rising edge of dataclk. the advantage of this method of reading data is that it is not being clocked out during a conversion and therefore conversion performance is not degraded. when reading data after the conversion is complete, with the highest frequency permitted for dataclk (15.15 mhz), and with the ad977a, the max imum possible throughput is approxi- mately 195 khz and not the rated 200 khz. for details on use of the tag input with this mode see the use of the tag feature section. busy r/c ext dataclk t 13 t 18 bit 15 (msb) bit 14 12 data sync t 14 t 12 0 3 14 15 16 t 1 t 2 t 24 t 21 bit 13 bit 1 bit 0 (lsb) tag 0 tag 1 t 23 tag 0 tag 1 tag 2 tag 3 tag 15 tag 16 tag 17 t 18 tag 18 tag figure 4. conversion and read timing using an external discontinuous data clock (ext/ int set to logic high, cs set to logic low)
ad977/ad977a C10C rev. d external discontinuous clock data read during conversion no sync output generated figure 5 illustrates the method by which data from conversion n-1 can be read during conversion n while using a discon- tinuous external clock, without the generation of a sync out- put. after a conversion is initiated, indicated by busy going low, the result of the previous conversion can be read while cs is low and r/ c is high. in this mode cs can be tied low. the msb will be valid on the 1st falling edge and the 2nd rising edge of dataclk. the lsb will be valid on the 16th falling edge and the 17th rising edge of dataclk. a minimum of 16 clock pulses are required for dataclk if the receiving device will be latching data on the falling edge of dataclk. a mini- mum of 17 clock pulses are required for dataclk if the receiving device will be latching data on the rising edge of dataclk. approximately 40 ns after the 17th rising edge of dataclk (if provided) the data output pin will reflect the state of the tag input pin during the first rising edge of dataclk. for both the ad977 and the ad977a the data should be clocked out during the first half of busy so not to degrade conversion performance. for the ad977 this requires use of a 4.8 mhz dataclk or greater with data being read out as soon as the conversion process begins. for the ad977a it requires use of a 10 mhz dataclk or greater. it is not recommended that data be shifted through the tag input in this mode as it will certainly result in clocking of data during the second half of the conversion. external discontinuous clock data read after conversion with sync output generated figure 6 illustrates the method by which data from conversion n can be read after the conversion is complete using a discon- tinuous external clock, with the generation of a sync output. what permits the generation of a sync output is a transition of dataclk while either cs is high or while both cs and r/ c are low. after a conversion is complete, indicated by busy returning high, the result of that conversion can be read while cs is low and r/ c is high. in this mode cs can be tied low. in figure 6 clock pulse #0 is used to enable the generation of a sync pulse. the sync pulse is actually clocked out approxi- mately 40 ns after the rising edge of clock pulse #1. the sync pulse will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. the msb will be valid on the falling edge of clock pulse #2 and the rising edge of clock pulse #3. the lsb will be valid on the falling edge of clock pulse #17 and the rising edge of clock pulse #18. approximately 40 ns after the rising edge of clock pulse #18 the data output pin will reflect the state of the tag input pin during the rising edge of clock pulse #2. the advantage of this method of reading data is that it is not being clocked out during a conversion and there- fore conversion performance is not degraded. when reading data after the conversion is complete, with the highest frequency permitted for dataclk (15.15 mhz), and with the ad977a, the maximum possible throughput is approximately 195 khz and not the rated 200 khz. for details on use of the tag input with this mode see the use of the tag input section. r/c busy ext dataclk t 13 t 15 bit 15 (msb) bit 14 12 data sync t 14 t 12 01516 t 22 bit 0 (lsb) t 18 t 1 t 21 t 2 t 18 t 20 figure 5. conversion and read timing for reading previous conversion results during a conversion using external discontinuous data clock (ext/ int set to logic high, cs set to logic low)
ad977/ad977a C11C rev. d external discontinuous clock data read during conversion with sync output generated figure 7 illustrates the method by which data from conversion n-1 can be read during conversion n while using a discon- tinuous external clock, with the generation of a sync output. what p ermits the generation of a sync output is a transition of dataclk while either cs is high or while both cs and r/ c are low. in figure 7 a conversion is initiated by taking r/ c low with cs tied low. while this condition exists a transition of dataclk, clock pulse #0, will enable the generation of a sync pulse. less then 83 ns after r/ c is taken low the busy output will go low to indicate that the conversion process has began. figure 7 shows r/ c then going high and after a delay of greater than 15 ns (t 15 ) clock pulse #1 can be taken high to request the sync output. the sync output will appear approximately 40 ns after this rising edge and will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. the msb will be valid approximately 40 ns after the rising edge of clock pulse #2 and can be latched off either the falling edge of clock pulse #2 or the rising edge of clock pulse #3. the lsb will be valid on the falling edge of clock pulse #17 and the ri sing edge of clock pulse #18. approximately 40 ns after the rising edge of clock pulse #18, the data output pin will reflect the state of the tag input pin during the rising edge of clock pulse #2. busy r/c ext dataclk t 13 bit 15 (msb) bit 14 12 data sync t 14 t 12 0 3 17 18 t 2 t 17 bit 0 (lsb) tag 0 tag 1 tag 0 tag 1 tag 2 tag 16 tag 17 tag 18 t 18 tag 19 tag tag 2 4 t 15 t 15 t 15 t 12 t 18 t 24 t 23 figure 6. conversion and read timing using an external discontinuous data clock (ext/ int set to logic high, cs set to logic low) busy r/c ext dataclk t 13 t 15 bit 15 (msb) bit 14 12 data sync t 14 t 12 0 318 t 1 t 12 bit 0 (lsb) tag 0 t 22 t 15 t 20 t 2 t 17 t 18 t 18 figure 7. conversion and read timing for reading previous conversion results during a conversion using external discontinuous data clock (ext/ int set to logic high, cs set to logic low)
ad977/ad977a C12C rev. d for both the ad977 and the ad977a the data should be clocked out during the first half of busy so not to degrade conversion performance. for the ad977 this requires use of a 4.8 mhz dataclk or greater, with data being read out as soon as the conversion process begins. for the ad977a it requires use of a 10 mhz dataclk or greater. it is not recommended that data be shifted through the tag input in this mode as it will certainly result in clocking of data during the second half of the conversion. external continuous clock data read after conversion with sync output generated figure 8 illustrates the method by which data from conversion n can be read after the conversion is complete using a con- tinuous external clock, with the generation of a sync output. what perm its the generation of a sync output is a transition of dataclk while either cs is high or while both cs and r/ c are low. with a continuous clock the cs pin cannot be tied low as it could be with a discontinuous clock. use of a continuous clock, while a conversion is occurring, can increase the dnl and transition noise of the ad977/ad977a. after a conversion is complete, indicated by busy returning high, the result of that conversion can be read while cs is low and r/ c is high. in figure 8 clock pulse #0 is used to enable the generation of a sync pulse. the sync pulse is actually c locked out approximately 40 ns after the rising edge of clock pulse #1. the sync pulse will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. the msb will be valid on the falling edge of clock pulse #2 and the rising edge of clock pulse #3. the lsb will be valid on the falling edge of clock pulse #17 and the rising edge of clock pulse #18. approximately 50 ns after the rising edge of clock pulse #18 the data output pin will reflect the state of the tag input pin during the rising edge of clock pulse #2. when reading data after the conversion is complete, with the highest frequency permitted for dataclk (15.15 mhz) and, with the ad977a, the maximum possible throughput is approxi- mately 195 khz and not the rated 200 khz. for details on use of the tag input with this mode see the use of the tag input section. figure 8. conversion and read timing using an external continuous data clock (ext/ int set to logic high) cs busy r/c bit 15 (msb) bit 14 t 2 tag 2 bit 0 (lsb) tag 0 tag 1 tag 0 tag 1 tag 2 tag 16 tag 17 tag 18 tag 19 t 13 0 t 14 t 12 1 2 3 4 17 18 t 1 t 15 t 16 t 17 t 19 t 24 t 12 t 23 t 18 t 18 t 16 ext dataclk tag data sync
ad977/ad977a C13C rev. d external continuous clock data read during conversion with sync output generated figure 9 illustrates the method by which data from conversion n-1 can be read during conversion n while using a continu- ous external clock with the generation of a sync output. what permits the generation of a sync output is a transition of dataclk w hile either cs is high or while both cs and r/ c are low. with a continuous clock the cs pin cannot be tied low as it could be with a discontinuous clock. use of a continuous clock while a conversion is occurring can increase the dnl and transition noise of the ad977/ad977a. in figure 9 a conversion is initiated by taking r/ c low with cs held low. while this condition exists a transition of dataclk, clock pulse #0, will enable the generation of a sync pulse. less then 83 ns after r/ c is taken low the busy output will go low to indicate that the conversion process has began. figure 9 shows r/ c then going high and after a delay of greater than 15 ns (t 15 ), clock pulse #1 can be taken high to request the sync output. the sync output will appear approximately 50 ns after this rising edge and will be valid on the falling edge of clock pulse #1 and the rising edge of clock pulse #2. the msb will be valid approximately 40 ns after the rising edge of clock pulse #2 and can be latched off either the falling edge of clock pulse #2 or the rising edge of clock pulse #3. the lsb will be valid on the falling edge of clock pulse #17 and the rising edge of clock pulse #18. approximately 40 ns after the rising edge of clock pulse #18, the data output pin will reflect the state of the tag input pin during the rising edge of clock pulse #2. for both the ad977 and the ad977a the data should be clocked out during the 1st half of busy so as not to degrade conversion performance. for the ad977 this requires use of a 4.8 mhz dataclk or greater with data being read out as soon as the conversion process begins. for the ad977a it requires use of a 10 mhz dataclk or greater. cs busy r/c ext dataclk bit 15 (msb) 1 data sync 03 bit 0 (lsb) tag 0 tag 1 tag 0 tag 2 t 13 t 14 t 12 t 19 18 t 15 t 16 t 1 t 20 t 2 t 17 t 12 t 18 t 23 t 24 t 18 tag 2 tag 1 tag 16 tag 17 tag 18 tag 19 figure 9. conversion and read timing for reading previous conversion results during a conversion using an external continuous data clock (ext/ int set to logic high)
ad977/ad977a C14C rev. d table i. ad977a analog input configuration input voltage connect r1 in connect r2 in connect r3 in input range via 200 to via 100 to to impedance 10 v v in agnd 2.5 v 11.5 k ? 5 v agnd v in 2.5 v 6.7 k ? 3.3 v v in v in 2.5 v 5.4 k ? 0 v to 10 v agnd v in agnd 6.7 k ? 0 v to 5 v agnd agnd v in 5.0 k ? 0 v to 4 v v in agnd v in 5.4 k ? table ii. ad977 analog input configuration input voltage connect r1 in connect r2 in connect r3 in input range via 200 to via 100 to to impedance 10 v v in agnd cap 22.9 k ? 5 v agnd v in cap 13.3 k ? 3.3 v v in v in cap 10.7 k ? 0 v to 10 v agnd v in agnd 13.3 k ? 0 v to 5 v agnd agnd v in 10.0 k ? 0 v to 4 v v in agnd v in 10.7 k ? analog inputs the ad977/ad977a is specified to operate with six full-scale analog input ranges. connections required for each of the three analog inputs, r1 in , r2 in and r3 in , and the resulting full-scale ranges, are shown in table i and table ii. the nominal input impedance for each analog input range is also shown. table iii shows the output codes for the ideal input voltages of each of the six analog input ranges. the analog input section has a 25 v overvoltage protection on r1 in and r2 in . since the ad977/ad977a has two analog grounds it is important to ensure that the analog input is refer- enced to the agnd1 pin, the low current ground. this will minimize any problems associated with a resistive ground drop. it is also important to ensure that the analog input of the ad977/ad977a is driven by a low impedance source. with its primarily resistive analog input circuitry, the adc can be driven by a wide selection of general purpose amplifiers. to best match the low distortion requirements of the ad977/ ad977a, care should be taken in the selection of the drive cir- cuitry op amp. figure 10 shows the simplified analog input section for the ad977/ad977a. since the ad977/ad977a can operate with an internal or external reference, and several different analog input ranges, the full-scale analog input range is best represented with a voltage that spans 0 v to v ref across the 40 pf sampling capacitor. the onboard resistors are laser trimmed to ratio match for adjustment of offset and full-scale error using fixed external resistors. the configurations shown in figures 12 and 13 are required to obtain the data sheet specifications for offset and full-scale error. the external fixed resistors are used during factory calibration so that a single 5 v supply can be used to bias the hardware trim circuitry. with the hardware adjust circuits shown in figures 12 and 13, offset and full-scale error can be trimmed to zero. refer to the offset and gain adjust section. if larger offset and full-scale errors are permitted, or if soft- ware calibration is used, the external resistors can be omit- ted. t able iv shows the resultant input ranges and offset and full-scale errors. using the ad977a with bipolar input ranges the connection diagrams in figure 11 show a buffer amplifier required for bipolar operation of the ad977a when using the internal reference. the buffer amplifier is required to isolate the cap pin from the signal dependent current in the r3 in pin. a high speed op amp such as the ad8031 can be used with a single 5 v power supply without degrading the performance of the ad977a. the buffer must have good settling characteristics and provide low total noise within the input bandwidth of the ad977a. r1 in r2 in r3 in ref 4k agnd2 cap agnd1 ad977/ad977a 20k /10k 2.5v reference 10k /5k 5k /2.5k 20k /10k 40pf switched cap adc figure 10. ad977/ad977a simplified analog input
ad977/ad977a C15C rev. d table iii. output codes and ideal input voltages digital output two? complement straight binary description analog input (sb/ btc low) (sb/ btc high) full-scale range 10 v 5 v 3.33 v 0 v to 10 v 0 v to 5 v 0 v to 4 v least significant bit 305 v 153 v 102 v 153 v 76 v 61 v +full scale (fsC1 lsb) 9.999695 v 4.999847 v 3.333231 v 9.999847 v 4.999924 v 3.999939 v 0111 1111 1111 1111 1111 1111 1111 1111 midscale 0 v 0 v 0 v 5 v 2.5 v 2 v 0000 0000 0000 0000 1000 0000 0000 0000 one lsb below midscale C305 v C153 v C102 v 4.999847 v 2.499924 v 1.999939 v 1111 1111 1111 1111 0111 1111 1111 1111 Cfull scale C10 v C5 v C3.333333 v 0 v 0 v 0 v 1000 0000 0000 0000 0000 0000 0000 0000 table iv. input ranges, offset and full-scale errors without external resistors ad977 offset error full-scale error ad977a offset error full-scale error input range a/b/c grade a/b/c grade input range a/b/c grade a/b/c grade C9.890 v to 9.90 v 25 mv/ 25 mv 0.75%/ 0.50% C9.800 v to 9.970 v 40 mv/ 40 mv 0.80%/ 0.55% C4.943 v to 4.995 v 25 mv/ 25 mv 0.75%/ 0.50% C4.900 v to 4.985 v 40 mv/ 40 mv 0.80%/ 0.55% C3.295 v to 3.330 v 25 mv/ 25 mv 0.75%/ 0.50% C3.267 v to 3.323 v 40 mv/ 40 mv 0.80%/ 0.55% 0.008 v to 9.946 v 10 mv/ 10 mv 0.75%/ 0.50% 0.007 v to 9.893 v 10 mv/ 10 mv 0.75%/ 0.50% 0.004 v to 5.023 v 10 mv/ 10 mv 0.75%/ 0.50% 0.004 v to 5.039 v 10 mv/ 10 mv 0.75%/ 0.50% 0.003 v to 4.010 v 10 mv/ 10 mv 0.75%/ 0.50% 0.003 v to 4.016 v 10 mv/ 10 mv 0.75%/ 0.50% 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977a ad8031 200 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977a v in 100 ad8031 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977a ad8031 figure 11. ad977a bipolar input co nfiguration using the internal reference; (a) v in = 10 v, (b) v in = 5 v, (c) v in = 3.33 v a. c. b.
ad977/ad977a C16C rev. d 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977 576k 50k 50k 5v 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977 576k 50k 50k 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977 576k 50k 50k bipolar connection for ad977 input range standard connection without offset and gain adjust standard connection with offset and gain adjust 10v 5v 3.33v 5v 5v 5v 5v 5v figure 12. ad977 bipolar analog input configuration
ad977/ad977a C17C rev. d 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977/ ad977a 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977/ ad977a 576k 50k 5v 50k 5v 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977/ ad977a 200 v in 33.2k 2.2 f r1 in r2 in ref agnd2 cap agnd1 ad977/ ad977a 576k 50k 5v 50k 5v 100 r3 in 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977/ ad977a 200 v in 100 33.2k 2.2 f 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977/ ad977a 576k 50k 5v 50k 5v unipolar connection for ad977a and ad977 input range standard connection without offset and gain adjust standard connection with offset and gain adjust 0v?0v 0v?v 0v?v + 2.2 f figure 13. ad977/ad977a unipolar analog input configuration
ad977/ad977a C18C rev. d voltage reference the ad977/ad977a has an on-chip temperature compensated bandgap voltage reference that is factory trimmed to 2.5 v 20 mv. the accuracy of the ad977/ad977a over the speci- fied temperature ranges is dominated by the drift performance of the voltage reference. the on-chip voltage reference is laser- trimmed to provide a typical drift of 7 ppm/ c. this typical drift characteristic is shown in figure 14, which is a plot of the change in reference voltage (in mv) versus the change in tem- peraturenotice the plot is normalized for zero error at 25 c. if improved drift performance is required, an external reference such as the ad780 should be used to provide a drift as low as 3 ppm/ c. in order to simplify the drive requirements of the voltage reference (internal or external), an onboard reference buffer is provided. the output of this buffer is provided at the cap pin and is available to the user; however, when externally loading the reference buffer, it is important to make sure that proper precautions are taken to minimize any degradation in the adcs performance. figure 15 shows the load regulation of the reference buffer. notice that this figure is also normalized so that there is zero error with no dc load. in the linear region, the output impedance at this point is typically 1 ? . because of this 1 ? output impedance, it is important to minimize any ac or degrees celsius 55 1mv/div 25 125 figure 14. reference drift load current 5ma/div dv on cap pin 10mv/div source capability sink capability figure 15. cap pin load regulation input dependent loads that will lead to increased distortion. any dc loads will simply act as a gain error. although the typi- cal characteristic of figure 15 shows that the ad977/ad977a is capable of driving loads greater than 15 ma, it is recom- mended that the steady state current not exceed 2 ma. using an external reference in addition to the on-chip reference, an external 2.5 v refer- ence can be applied. when choosing an external reference for a 16-bit application, however, careful attention should be paid to noise and temperature drift. these critical specifications can have a significant effect on the adc performance. figures 16a and 16b show the ad977/ad977a used in bipolar mode with the ad780 voltage reference applied to the ref pin. it is important to note that in figure 16a the r3 in pin is connected to the cap pin whereas in figure 16b the r3 in pin of the ad977a is returned to the output of the external refer- ence. the ad780 is a bandgap reference that exhibits ultralow drift, low initial error and low output noise. in figure 16b, the value for c1 is only applicable to applications using the ad780. in applications using a different external reference a different value for c1 may be required. for low power applica- tions, the ref192 provides a low quiescent current, high accu racy and low temperature drift solution. 200 v in 33.2k c2 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977 v ana c4 0.1 f c1 2.2 f c3 1 f 4 gnd 6 v out v in temp ad780 3 2 0.1 f 5v 100 figure 16a. ad780 external reference to ad977 config- ured for 10 v input range 200 v in 33.2k c2 2.2 f r1 in r2 in r3 in ref agnd2 cap agnd1 ad977a v ana c4 0.1 f c1 330 f * c3 1 f 4 gnd 6 v out v in temp ad780 3 2 0.1 f 5v 100 * esr at 100khz must be less than 0.3 . recommend kemet t495 series or sanyo 6sa330m. figure 16b. ad780 external reference to ad977a config- ured for 10 v input range
ad977/ad977a C19C rev. d offset and gain adjustment the ad977/ad977a is factory trimmed to minim ize gain, offset and linearity errors. in some applications, where the ana- log input signal is required to meet the full dynamic range of the adc, the gain and offset errors need to be externally trimmed to zero. figures 12 and 13 show the required trim circuitry to correct for these offset and gain errors. where adjustment is required, offset error must be corrected before gain error. to achieve this in the bipolar input configura- tion, trim the offset potentiometer with the input voltage set to 1/2 lsb below ground. then adjust the potentiometer until the major carry transition is located between 1111 1111 1111 1111 and 0000 0000 0000 0000. to adjust the gain error, an analog signal should be input at either the first code transition (adc negative full scale) or the last code transition (adc positive full scale). thus, to adjust for full-scale error, an input voltage of fs/2 C 3/2 lsbs can be applied to v in , and the gain potentiom- eter should be adjusted until the output code flickers between the last positive code transition 0111 1111 1111 1111 and 0111 1111 1111 1110. should the first code transition need adjust- ing, the trim procedure should consist of applying an analog input signal of Cfs/2 + 1/2 lsb to the v in input and adjust- ing the trim until the output code flickers between 1000 0000 0000 0000 and 1000 0000 0000 0001. ac performance the ad977/ad977a is fully specified and tested for dynamic performance specifications. the ac parameters are required for signal processing applications such as speech recognition and spectrum analysis. these applications require information on the adcs effect on the spectral content of the input signal. hence, the parameters for which the ad977/ad977a is specified include s/(n+d), thd and spurious free dynamic r ange. these terms are discussed in greater detail in the following sections. as a general rule, it is recommended that the results from sev- eral conversions be averaged to reduce the effects of noise and thus improve parameters such as s/(n+d) and thd. the ac performance of the ad977/ad977a can be optimized by operat- ing the adc at its maximum sampling rate of 100 khz/200 khz and digitally filtering the resulting bit stream to the desired signal bandwidth. by distributing noise over a wider frequency range the noise density in the frequency band of interest can be reduced. for example, if the required input bandwidth is 50 khz, frequency khz 0 10 0 100 10 20 30 40 40 70 130 20 30 60 50 amplitude db 90 120 80 110 100 50 60 70 80 90 95 5 1525354555657585 5280 point fft f sample = 200khz f in = 20khz, 0db snrd = 86db thd = 101db figure 17. fft plot the ad977/ad977a could be oversampled by a factor of 2/4. this would yield a 3/6 db improvement in the effective snr performance. dc performance the factory calibration scheme used for the ad977/ad977a compensates for bit weight errors that may exist in the capacitor array. the mismatch in capacitor values is adjusted (using the calibration coefficients) during a conversion resulting in excel- lent dc linearity performance. figures 18, 19, 20, 21, 22 and 23, respect ively, show typical inl, typical dnl, typical positive and negative inl and dnl distribution plots for the ad977/ad977a at 25 c. a histogram test is a statistical method for deriving an a/d converters differential nonlinearity. a ramp input is sampled by the adc and a large number of conversions are taken at each voltage level, averaged then stored. the effect of averaging is to reduce the transition noise by 1/n. if 64 samples are averaged at each point, the effect of transition noise is reduced by a factor of 8, i.e., a transition noise of 0.8 lsbs rms is reduced to 0.1 lsbs rms. t heoretically the codes, during a test of dnl, would all be the same size and therefore have an equal number of occurrences. a code with an average number of occurrences would have a dnl of 0. a code that is different from the average would have a dnl that was either greater or less than zero lsb. a dnl of C1 lsb indicates that there is a missing code present at the 16-bit level and that the adc exhibits 15- bit performance. output code k 066 5 101520253035 2.0 2.0 0 0.5 1.0 1.5 1.0 0.5 1.5 40 45 50 55 60 100% lsb figure 18. inl plot output code k 066 5 101520253035 2.0 2.0 0 0.5 1.0 1.5 1.0 0.5 1.5 40 45 50 55 60 100% lsb figure 19. dnl plot
ad977/ad977a C20C rev. d positive inl lsb 0 50 10 25 20 15 40 35 45 number of units 5 0 30 0.2 0.3 0.4 0.5 0.6 0.8 0.9 1 1.1 1.2 2.9 1.4 1.5 1.6 1.7 1.8 2 2.1 2.2 2.3 2.4 2.6 2.7 2.8 figure 20. typical positive inl distribution (999 units) negative inl lsb 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 60 30 20 50 number of units 10 0 40 0.1 figure 21. typical negative inl distribution (999 units) positive dnl lsb 60 20 number of units 0 40 80 100 120 0.02 0.10 0.19 0.27 0.36 0.44 0.52 0.61 0.69 0.77 0.86 0.94 1.02 1.11 1.19 1.27 1.36 1.44 1.53 1.61 1.69 1.78 1.86 1.94 2.03 figure 22. typical positive dnl distribution (999 units) 60 30 20 50 number of units 10 0 40 1.17 1.12 1.02 0.92 negative dnl lsb 1.07 0.97 70 80 90 1.22 0.87 0.82 0.78 0.73 0.68 0.63 0.58 0.53 0.48 0.43 0.38 0.33 0.28 0.23 0.18 0.14 0.09 0.04 figure 23. typical negative dnl distribution (999 units) snr+d (db) for ad977a 90 80 70 60 50 40 30 20 10 sinad (db) for v in = 0db 1 10 100 1000 input signal frequency khz snr+d (db) for ad977 figure 24. s/(n+d) vs. input frequency temperature c 110 100 80 75 150 50 sfdr, s/n+d db 25 0 25 50 75 100 125 90 105 95 85 80 90 110 100 85 95 105 sfdr thd snrd thd db figure 25. ac parameters vs. temperature
ad977/ad977a C21C rev. d dc code uncertainty ideally, a fixed dc input should result in the same output code for repetitive conversions; however, as a consequence of un avoid- able circuit noise within the wideband circuits of the adc, a range of output codes may occur for a given input voltage. thus, when a dc signal is applied to the ad977/ad977a input and 10,000 conversions are recorded, the result will be a distri- bution of codes as shown in figure 26. this histogram shows a bell shaped curve consistent with the gaussian nature of thermal noise. the histogram is approximately seven codes w ide. the standard deviation of this gaussian distribution results in a code transition noise of 1 lsb rms. 4000 3500 0 3 2000 1500 1000 500 3000 2500 2 10 1 2 3 4 figure 26. histogram of 10,000 conversions of a dc input use of the tag input the ad977/ad977a provides a tag input pin for cascading multiple converters together. this feature is useful for reducing component count in systems where an isolation barrier must be crossed and is also useful for systems with a limited capacity for interfacing to a large number of converters. the tag feature only works in the external clock mode and requires that the data output of a upstream device be con- nected to the tag input of an downstream device. an example of the concatenation of two devices is shown in figure 27 and their resultant output is shown in figure 28. in figure 27, the paralleled r/ c ensures that each ad977/ ad977a will simultaneously sample their inputs. in figure 28, a null bit is shown between each 16-bit word associated with each adc in the serial data output stream. this is the result of a minimum value for external data clock to data valid delay (t 18 ) that is greater than the tag valid setup time (t 23 ). in other words, when you concatenate two or more ad977/ad977as the msb on the downstream device will not be present on the tag input of the upstream device in time to meet the setup time requirement of the tag input. if the serial data stream is going to a parallel port of a micro- processor that is also providing the serial data clock, then the microprocessors firmware can be written to throw away the null bit. if the serial data stream is going to a serial port then external glue logic will have to be added to make the interface work. if the serial port has a sync input then this can be used to throw away the null bit if the sync input is toggled each time the null bit appears. if the application does not require simultaneous sampling, the null bit can be completely avoided by delaying the r/ c signal of each upstream device by one clock cycle with respect to its immediate downstream device. this bit time delay can be accom- plished through a d-type flip-flop that delays the r/ c signal at its d-input by one cycle of the serial data clock that is at its clock input. data out dclk in r/ in in tag data dclk ad977/ad977a #2 (upstream) ad977/ad977a #1 (downstream) tag data dclk cs r/c cs r/c figure 27. two ad977/ad977as utilizing tag it is not recommended that the tag feature be used with the read during convert mode because this will require data to be clocked out during the second half of the conversion process. it is recommended that the read after convert mode be used in an application that wants to take advantage of the tag feature. to improve the data throughput a combination of the two data read methods can be used and is described as follows. if two or more ad977/ad977as are to have their data output concatenated together in a single data stream, and if data throughput is to be maximized, a system could be designed such that the upstream device data is read during the first half of its conversion process and the remainder of the d ownstream devices read during the time between conversions. assume three ad977as are to have their data concatenated. assume the further most downstream device is referred to as device #1 and the further most upstream device as #3. each device is driven from a com- mon dataclk and r/ c control signal, the cs input of each device is tied to ground. the three busy outputs should be ord together to form a composite busy . after the conversion is complete, as indicated by the composite busy going high, an external, normally low, 15.15 mhz dataclk can be toggled 34 times to first read the data first from device #3 and then from device #2. when the composite busy goes low to indicate the beginning of the conversion process the external data- clk can be toggled 17 times to read the data from device #1 during the first half of the conversion process. using this tech- nique it would be possible to read in the data from the three devices in approximately 6.4 s for a throughput of approxi- mately 156 khz the receiving device would have to deal with the null bit between data from device #2 and #3. the receiving device would also have to be capable of starting and stopping the external dataclk at the appropriate times. the tag input, when unused, should always be tied either high or low and not be allowed to float.
ad977/ad977a C22C rev. d data null bit device data #1 device data #2 15 0 15 dclk r/ c busy figure 28. tag timing diagram for two concatenated ad977/ad977as power-down feature the ad977/ad977a has analog and reference power-down capability through the pwrd pin. when the pwrd pin is taken high, the power consumption drops from a maximum value of 100 mw to a typical value of 50 w. when in the power-down mode the previous conversion results are still avail- able in the internal registers and can be read out providing it has not already been shifted out. when used with an external reference, connected to the ref pin and a 2.2 f capacitor, connected to the cap pin, the power up recovery time is typically 1 ms. this typical value of 1 ms for recovery time depends on how much charge has de cayed from the external 2.2 f capacitor on the cap pin and assumes that it has decayed to zero. the 1 ms recovery time has been specified such that settling to 16-bits has been achieved. when used with the internal reference, the dominant time con- stant for power-up recovery is determined by the external capacitor on the ref pin and the internal 4k impedance seen at that pin. an external 2.2 f capacitor is recommended for the ref pin. considerations when using multiplexed inputs consideration must be given to the effect on a/d performance in applications that require the use of analog multiplexers or analog switches to interface multiple signals to the ad977/ad977a. the nonzero on resistance of a multiplexer or switch, at the input to the ad977/ad977a, will increase the system offset and gain error. as an example, consider the ad977 configured for an input voltage range of 10 v dc. for every 5 ? of source impe dance (in addition to the required external 200 ? input resistor) an offset error of 1 lsb would be introduced and the positive gain error would increase by an added 0.00375% of full s cale. this error, due to nonzero source impedance, can be cor- rected through a hardware or software system level calibration, but will only be valid at the temperature and input voltage present at the time of calibration. another factor to consider is that most analog multiplexers and switches exhibit a nonlinear relationship between input signal level and on resistance. this will introduce added distortion products that will degrade thd, s/(n+d) and inl. for these reasons it is recommended that an appropriate buffer be used between the output of the multi plexer and the input of the ad977. when switching the input to the multiplexer, and subsequently the input to the ad977, it is recommended that the transition be made to occur either immediately after the current conver- sion is complete or shortly after the beginning of a conversion. microprocessor interfacing the ad977/ad977a is ideally suited for traditional dc mea- surem ent applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. the ad977/ad977a is designed to interface with a general purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad977/ad977a to prevent digital noise from coupling into the adc. the following sections illustrate the use of the ad977/ad977a with an spi equipped microcontroller and the adsp-2181 signal processor. spi interface figure 29 shows a general interface diagram between the ad977/ad977a and an spi equipped microcontroller. this interface assumes that the convert pulses will originate from the microcontroller and that the ad977/ad977a will act as the slave device. the convert pulse could be initiated in response to an internal timer interrupt. the reading of output data, one byte at a time, if necessary, could be initiated in response to the end- of-conversion signal ( busy going high). +5v sdi sck i/o port irq spi dataclk data tag ad977/ ad977a ext/int cs busy r/c figure 29. ad977/ad977a to spi interface adsp-2181 interface figure 30 shows an interface between the ad977/ad977a and the adsp-2181 digital signal processor. the ad977/ad977a is configured for the internal clock mode (ext/ int = 0) and will therefore act as the master device. the convert command is shown generated from an external oscillator in order to provide a low jitter signal appropriate for both dc and ac measurements. because the sport, within the adsp-2181, will be seeing a discontinuous external clock, some steps are required to ensure that the serial port is properly synchronized to this clock during each d ata read operation. the recommended procedure to ensure this is as follows, C enable sport0 through the system control register C set the sclk divide register to zero C setup pf0 and pf1 as outputs by setting bits 0 and 1 in pftype C force rfs0 low through pf0. the receive frame sync signal has been programmed active high C enable ad977/ad977a by forcing cs = 0 through pf1 C enable sport0 receive interrupt through the imask register C wait for at least one full conversion cycle of the ad977/ad 977a and throw away the received data C disable the ad977/ad977a by forcing cs = 1 through pf1 C wait for a period of time equal to one conversion cycle C force rfs0 high through pf0 C enable the ad977/ad977a by forcing cs = 0 through pf1
ad977/ad977a C23C rev. d the adsp-2181 sport0 will now remain synchronized to the external discontinuous clock for all subsequent conversions. dr0 sclk0 pf1 adsp-2181 dataclk data tag ad977/ ad977a oscillator rfs0 pf0 sport0 cntrl reg = 0x300f ext/int cs r/c figure 30. ad977/ad977a to adsp-2181 interface power supplies and decoupling the ad977/ad977a has two power supply input pins. v ana and v dig provide the supply voltages to the analog and digital portions, respectively. v ana is the 5 v supply for the on-chip analog circuitry, and v dig is the 5 v supply for the on-chip digital circuitry. the ad977/ad977a is designed to be inde- pendent of power supply sequencing and thus free from supply voltage induced latchup. with high performance linear circuits, changes in the power supplies can result in undesired circuit performance. optimally, well regulated power supplies should be chosen with less than 1% ripple. the ac output impedance of a power supply is a complex function of frequency and will generally increase with frequency. thus, high frequency switching, such as that encoun- tered with digital circuitry, requires the fast transient currents that most power supplies cannot adequately provide. such a situation results in large voltage spikes on the supplies. to com- pensate for the finite ac output impedance of most supplies, charge reserves should be stored in bypass capacitors. this will effectively lower the supplies impedance presented to the ad977/ad977a v ana and v dig pins and reduce the magnitude of these spikes. decoupling capacitors, typically 0.1 f, should be placed close to the power supply pins of the ad977/ad977a to minimize any inductance between the capacitors and the v ana and v dig pins. the ad977/ad977a may be operated from a single 5 v supply. when separate supplies are used, however, it is benefi- cial to have larger capacitors, 10 f, placed between the logic supply (v dig ) and digital common (dgnd) and between the analog supply (v ana ) and the analog common (agnd2). additionally, 10 f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. in systems where the device will be subjected to harsh environmental noise, additional decoupling may be required. grounding the ad977/ad977a has three ground pins; agnd1, agnd2 and dgnd. the analog ground pins are the high q uality ground reference points and should be connected to the system analog common. agnd2 is the ground to which most internal adc analog signals are referenced. this ground is most sus- ceptible to current induced voltage drops and thus must be connected with the least resistance back to the power supply. agnd1 is the low current analog supply ground and should be the analog common for the external reference, input op amp drive circuitry and the input resistor divider circuit. by applying the inputs referenced to this ground, any ground variations will be offset and have a minimal effect on the resulting analog input to the adc. the digital ground pin, dgnd, is the reference point for all of the digital signals that control the ad977/ad977a. the ad977/ad977a can be powered with two separate power supplies or with a single analog supply. when the system digital supply is noisy, or fast switching digital signals are present, it is recommended to connect the analog supply to both the v ana and v dig pins of the ad977/ad977a and the system supply to the remaining digital circuitry. with this configuration, agnd1, agnd2 and dgnd should be connected back at the adc. when there is significant bus activity on the digital output pins, the digital and analog supply pins on the adc should be separated. this would eliminate any high speed digital noise from coupling back to the analog portion of the ad977/ ad977a. in this configuration, the digital ground pin dgnd should be connected to the system digital ground and be separate from the agnd pins. board layout designing with high resolution data converters requires careful attention to board layout. trace impedance is a significant issue. a 1.22 ma current through a 0.5 ? trace will develop a voltage drop of 0.6 mv, which is 2 lsbs at the 16-bit level over the 20 volt full-scale range. ground circuit impedances should be reduced as much as possible since any ground potential differ- ences between the signal source and the adc appear as an error voltage in series with the input signal. in addition to ground drops, inductive and capacitive coupling needs to be considered. this is especially true when high accuracy analog input signals share the same board with digital signals. thus, to minimize input noise coupling, the input signal leads to v in and the signal return leads from agnd should be kept as short as possible. in addition, power supplies should also be decoupled to filter out ac noise. analog and digital signals should not share a common path. each signal should have an appropriate analog or digital return routed close to it. using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. wide pc tracks, large gauge wire and ground planes are highly recom- mended to provide low impedance signal paths. separate analog and digital ground planes are also recommended with a single interconnection point to minimize ground loops. analog signals should be routed as far as possible from high speed digital sig- nals and should only cross them, if absolutely necessary, at right angles. in addition, it is recommended that multilayer pc boards be used with separate power and ground planes. when designing the separate sections, careful attention should be paid to the layout.
ad977/ad977a C24C rev. d outline dimensions dimensions shown in inches and (mm). c00913dC5C10/00 (rev. d) printed in u.s.a. 20-lead plastic dip (n-20) 20 110 11 1.060 (26.90) 0.925 (23.50) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 20-lead wide body (soic) (r-20) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 20 11 10 1 0.5118 (13.00) 0.4961 (12.60) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28-lead shrink small outline package (ssop) (rs-28) 28 15 14 1 0.407 (10.34) 0.397 (10.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.79) 0.066 (1.67) 0.0256 (0.65) bsc 0.078 (1.98) 0.068 (1.73) 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) 8 0

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